As network designers increase bandwidth, it is increasingly important to specify signal integrity standards for electrical physical interfaces, regardless of whether the interface is internal routing within an integrated circuit, a signal between circuits on printed circuit media, or an external signal such as that on an outdoor cable or optical fiber. Assuming the signals are digital, a problem that is becoming more difficult as data rates increase is the inability to control the propagation delay of a group of signals such that they arrive at their destinations simultaneously. A proposed solution is to multiplex individual digital signals into one “fast” serial data line, such that one transmitter, transmission line and receiver combine, transmit, propagate, and decode a large grouping of digital signals.
Although this multiplexing approach eliminates the synchronicity problem between bundles of signals, it invites other problems such as reception of the data by a receiver whose clock is not phase synchronous with the incoming high-speed data. To solve this problem, a process known as “clock recovery” is applied where the receiver generates a clock that is phase-synchronous with the incoming data stream. Since the clock recovery solution must be applied to systems or integrated circuits or “chips” that communicate with other systems or chips, it is necessary that companies developing these systems comply with the same industry-accepted standard. Similarly, companies who provide test equipment claiming test compliance must insure the accuracy of their measurements such that results obtained comply (or do not comply) with the same standards.
The methods and apparatus of the present application were developed and applied as a consequence of developing compliant clock recovery test equipment.
While investigating existing forms of clock recovery, it was found that current methods and commercial offerings were unable to provide the necessary accuracy to measure random and deterministic jitter in accordance with industry standards. Shortcomings include:                1.) The inability to acquire and lock to serial data patterns ranging from periodic to pseudo-random data streams.        2.) The inability to acquire and lock to serial data streams with low or sparse transition density.        3.) Vague or undefined phase lock loop characteristic (order, amplitude and phase response).        4.) In the case of specified phase lock loop characteristics, the tolerance of order, amplitude and phase response was too loose.        5.) Inability of systems to self-test or assert their PLL order, amplitude and phase response.        6.) Inability of systems to measure random and deterministic jitter tracked by the phase lock loop.        7.) Inability of systems to recover serial data at microwave frequency data rates.        
In view of the foregoing, there arises a need for an improved clock recovery method and apparatus. The following addresses and helps to solve and/or minimize the shortcomings of the prior art.